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27 3-27 features ? provides t1 clock at 1.544 mhz locked to input frame pulse ? sources cept (30+2) digital trunk/st-bus clock and timing signals locked to internal or external 8 khz signal ? ttl compatible logic inputs and outputs ? uncommitted 2-input nand gate ? single 5 volt power supply ? low power iso-cmos technology applications ? synchronization and timing control for t1 and cept digital trunk transmission links ? st- bus clock and frame pulse source description the MT8940 is a dual digital phase-locked loop providing the timing and synchronization signals for the t1 or cept transmission links and the st-bus. the ?rst pll provides the t1 clock (1.544 mhz) synchronized to the input frame pulse at 8 khz. the timing signals for the cept transmission link and the st-bus are provided by the second pll locked to an internal or an external 8 khz frame pulse signal. the MT8940 is fabricated in mitels iso-cmos technology. ordering information MT8940ae 24 pin plastic dip (600 mil) -40 c to +85 c figure 1 - functional block diagram f0i c12i ms0 ms1 ms2 ms3 c8kb c16i ai bi yo v dd v ss rst cvb cv encv f0b c4b c4o enc4o c2o c2o enc2o 2:1 mux variable clock control mode selection logic dpll #2 input selector clock generator frame pulse control 4.096 mhz clock control 2.048 mhz clock control dpll #1 issue 8 march 1997 MT8940 t1/cept digital trunk pll iso-cmos st-bus ? family
MT8940 iso-cmos 3-28 figure 2 - pin connections pin description pin # name description 1en cv variable clock enable (ttl compatible input) - this input (pulled internally to v dd ) directly controls the three states of cv (pin 22) under all modes of operation. when high, enables cv and when low, puts it in high impedance condition. it also controls the three states of cvb signal (pin 21) if ms1 is low. when en cv is high, the pin cvb is an output and when low, it is in high impedance state. however, if ms1 is high, cvb is always an input. 2 ms0 mode select 0 input (ttl compatible) - this input (pulled internally to v ss ) in conjunction with ms1 (pin 4) selects the major mode of operation for both dplls. (refer to tables 1 and 2). 3 c12i clock 12.355 mhz input (ttl compatible) - master clock input at 12.355 mhz 100ppm for dpll #1. 4 ms1 mode select-1 input (ttl compatible) - this input (pulled internally to v ss ) in conjunction with ms0 (pin 2) selects the major mode of operation for both dplls. (refer to tables 1 and 2) 5 f0i frame pulse input (ttl compatible) - this is the frame pulse input (pulled internally to v dd ) at 8 khz. the dpll #1 locks to the falling edge of this input to generate t1 (1.544 mhz) clock. 6 f0b frame pulse bidirectional (ttl compatible input and totem-pole output) - depending on the minor mode selected for the dpll #2, it provides the 8 khz frame pulse output or acts as an input (pulled internally to v dd ) to an external frame pulse. 7 ms2 mode select-2 input (ttl compatible) - this input (pulled internally to v dd ) in conjunction with ms3 (pin 17) selects the minor mode of operation for the dpll #2. (refer to table 3.) 8 c16i clock 16.388 mhz input (ttl compatible) - master clock input at 16.388 mhz 32 ppm for dpll #2. 9en c4o enable 4.096 mhz clock (ttl compatible input) - this active high input (pulled internally to v dd ) enables c4o (pin 11) output. when low, the output c4o is in high impedance condition. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 envc ms0 c12i ms1 f0i f0b ms2 c16i enc4o c8kb c4o vss vdd rst cv cvb yo bi ai ms3 enc2o c2o c2o c4b
iso-cmos MT8940 3-29 10 c8kb clock 8 khz- bidirectional (ttl compatible input and open drain output with 100k internal resistor to v dd ) - this is the 8 khz input signal on the rising edge of which dpll #2 locks during its normal mode. when dpll #2 is in single clock mode, this pin outputs an 8 khz signal provided by dpll #1, which is also connected internally to dpll #2. 11 c4o clock 4.096 mhz (three state output) - this is the inverse of the signal appearing on pin 13 ( c4b) at 4.096 mhz and has a rising edge in the frame pulse ( f0b) window. the high impedance state of this output is controlled by en c4o (pin 9). 12 v ss ground (0 volt) 13 c4b clock 4.096 mhz- bidirectional (ttl compatible input and totem-pole output) - when the mode select bit ms3 (pin 17) is high, it provides the 4.096 mhz clock output with the falling edge in the frame pulse ( f0b) window. when pin 17 is low, c4b is an input (pulled internally to v dd ) to an external clock at 4.096 mhz. 14 c2o clock 2.048 mhz (three state output) - this is the divide by two output of c4b (pin 13) and has a falling edge in the frame pulse ( f0b) window. the high impedance state of this output is controlled by en c2o (pin 16). 15 c2o clock 2.048 mhz (three state output) - this is the divide by two output of c4b (pin 13) and has a rising edge in the frame pulse ( f0b) window. the high impedance state of this output is controlled by en c2o (pin 16). 16 en c2o enable 2.048 mhz clock (ttl compatible input) - this active high input (pulled internally to v dd ) enables both c2o and c2o outputs (pins 14 and 15). when low, these outputs are in high impedance condition. 17 ms3 mode select 3 input (ttl compatible) - this input (pulled internally to v dd ) in conjunction with ms2 (pin 7) selects the minor mode of operation for dpll #2. (refer to table 3.) 18,19 ai, bi inputs a and b (ttl compatible) - these are the two inputs (pulled internally to v ss ) of the uncommitted nand gate . 20 y o output y (totem pole output) - output of the uncommitted nand gate. 21 cvb variable clock bidirectional (ttl compatible input and totem-pole output) - when acting as an output (ms1-low) during the normal mode of dpll #1, this pin provides the 1.544 mhz clock locked to the input frame pulse f0i (pin 5). when ms1 is high, it is an input (pulled internally to v dd ) to an external clock at 1.544 mhz or 2.048 mhz to provide the internal signal at 8 khz to dpll #2. 22 cv variable clock (three state output) - this is the inverse output of the signal appearing on pin 21, the high impedance state of which is controlled en cv (pin 1). 23 rst reset (schmitt trigger input) - this input (active low) evokes reset condition for the device. 24 v dd v dd (+5v) power supply. pin description (continued) pin # name description
MT8940 iso-cmos 3-30 functional description the MT8940 is a dual digital phase-locked loop providing the timing and synchronization signals to the interface circuits for t1 and cept (30+2) primary multiplex digital transmission links. as shown in figure 1, it has two digital phase-locked loops (dplls), associated output controls and the mode selection logic circuits. the two dplls, although similar in principle, operate independently to provide t1 (1.544 mhz) and cept (2.048 mhz) transmission clocks, and st-bus timing signals. the principle of operation behind the two dplls is shown in figure 3. a master clock is divided down to 8 khz where it is compared with the 8 khz input, and depending on the output of the phase comparison, the master clock frequency is corrected. the MT8940 achieves the frequency correction in both directions by using the master clock at a slightly higher frequency and dividing it unaltered or stretching its period (at two discrete instants in a frame) before the division depending on the phase comparison output. when the input frequency is figure 3 - dpll principle higher, the unchanged master clock is divided, thus effectively speeding-up the locally generated clock and eventually pulling it in synchronization with the input. if the input frequency is lower than the divided master clock, the period of the master clock is stretched by half a cycle, at two discrete instants in a phase sampling period. this introduces a total delay of one master clock period over the sampling duration, which is then divided to generate the local signal synchronous with the input. once the output is phase-locked to the active edge of the input, the circuit will maintain the locked condition as long as the input frequency is within the lock-in range ( 1.04 hz) of the dplls. the lock-in range is wide enough to meet the ccitt line rate speci?cation (1.544 mhz 130ppm and 2.048 mhz 50ppm) for the high capacity terrestrial digital service. the phase sampling is done once in a frame (8 khz) and the divisions are set at 8 and 193 for dpll #1, which locks on to the falling edge of the input at 8 khz to generate t1 (1.544 mhz) clock. although the phase sampling duration is the same for dpll #2, the divisions are set at 8 and 256 to provide the cept/st-bus clock at 2.048 mhz synchronized to the rising edge of the input signal (8 khz). the master clock source is speci?ed to be at 12.355 mhz 100 ppm for dpll #1 and 16.388 mhz 32 ppm for dpll #2 over the entire temperature range of operation. the inputs ms0 to ms3 are used to select the operating mode of the MT8940, see tables 1 to 4. all the outputs are individually controlled to the high impedance condition by their respective enable controls. the uncommitted nand gate is available for use in applications involving mitels mt8976/mh89760 (t1 interfaces) and mt8979/mh89790 (cept interfaces). modes of operation the operation of the MT8940 is categorized into major and minor modes. the major modes are de?ned for both dplls by the mode select pins ms0 and ms1. the minor modes are selected by ms2 and ms3, and are applicable only to dpll #2. there are no minor modes for dpll #1. major modes of the dpll #1 dpll #1 can be operated in three major modes as selected by ms0 and ms1 (table 1). when ms1 is low, it is in normal mode, which provides a t1 (1.544 mhz) clock signal locked to the falling edge of the input frame pulse f0i (8 khz). dpll#1 requires a master clock input of 12.355 mhz 100 ppm (c12i). in the second and third major modes (ms1 is high), dpll #1 is set to divide an external 1.544 mhz or 2.048 mhz signal applied at cvb (pin 21). the division can be set by ms0 to be either 193 (low) or 256 (high). in these modes, the 8 khz output is connected internally to dpll #2, which operates in single clock mode. major modes of the dpll #2 there are four major modes for dpll #2 selectable by ms0 and ms1, as shown in table 2. in all these modes dpll #2 provides the cept pcm 30 timing, and the st-bus clock and framing signals. in normal mode, dpll #2 provides the cept and st-bus compatible timing signals locked to the rising edge of the 8 khz input signal (c8kb). these master clock (12.355 mhz/ 16.388 mhz) frequency correction ? 8 output (1.544 mhz / input (8 khz) phase comparison ? 193 / ? 256 2.048 mhz)
iso-cmos MT8940 3-31 signals are the 4.096 mhz (c4o and c4b) and the 2.048 mhz (c2o and c2o) clocks, and the 8 khz note: x: indicates dont care table 1. major modes of the dpll #1 frame pulse ( f0b), which are derived from the 16.388 mhz master clock. this mode can also provide the st-bus timing and framing signals with the input (c8kb) tied high and the master clock set at 16.384 mhz. the dpll makes no correction in this con?guration and provides the timing signals compatible to the st-bus format without any jitter. in free-run mode, dpll #2 generates cept and st-bus timing and framing signals with no external inputs except the master clock set at 16.388 mhz. since the master clock source is set at a higher frequency than the nominal value, the dpll makes the necessary corrections to deliver the averaged timing signals compatible to the st-bus format. the operation of dpll #2 in single clock-1 mode is identical to single clock-2 mode, providing the cept and st-bus compatible timing signals synchronized to the internal 8 khz signal obtained from dpll#1 in divide mode. when single clock-1 mode is selected for dpll #2, it automatically selects the divide-1 mode for dpll #1, and thus, an external 1.544 mhz clock signal applied at cvb (pin 21) is divided by dpll #1 to generate the internal signal at 8 khz onto which dpll #2 locks. similarly when single clock-2 mode is selected, dpll #1 is in divide-2 mode, with an external signal of 2.048 mhz providing the internal 8 khz signal to dpll #2. in both these modes, this internal signal is available on c8kb (pin 10) and dpll #2 locks to its falling edge to provide the cept and st-bus compatible timing signals. this is in contrast to the normal mode where these timing signals are synchronized with the rising edge of the 8 khz signal on c8kb. minor modes of the dpll #2 the minor modes for dpll #2 depends upon the status of the mode select bits ms2 and ms3 (pins 7 and 17). table 2. major modes of the dpll #2 when ms3 is high, dpll #2 operates in any of the major modes as selected by ms0 and ms1. when ms3 is low, it overrides the major mode selected and dpll #2 accepts an external clock of 4.096 mhz on c4b (pin 13) to provide the 2.048 mhz clocks (c2o and c2o) and the 8 khz frame pulse ( f0b) compatible with the st-bus format. the mode select bit ms2, controls the signal direction of f0b (pin 6). when ms2 is low, f0b is an input for an external frame pulse at 8 khz. this table 3. minor modes of the dpll #2 input is effective only if ms3 is also low and c4b is accepting a 4.096 mhz external clock, which has a proper phase relationship with the external input on ms0 ms1 mode of operation function x 0 normal provides the t1 (1.544 mhz) clock synchronized to the falling edge of the input frame pulse ( f0i). 0 1 divide-1 dpll #1 divides the cvb input by 193. the divided output is connected to dpll #2. 1 1 divide-2 dpll #1 divides the cvb input by 256. the divided output is connected to dpll #2. ms0 ms1 mode of operation function 0 0 normal provides st-bus/cept timing signals locked to the rising edge of the 8khz input signal at c8kb. 1 0 free-run provides st-bus timing and framing signals with no external inputs, except the master clock. 0 1 single clock-1 provides the cept/st- bus compatible timing signals locked to the falling edge of the 8khz internal signal provided by dpll #1. 1 1 single clock-2 provides cept/st-bus timing signals locked to the falling edge of the 8khz internal signal provided by dpll #1. ms2 ms3 functional description 1 1 provides st-bus 4.096 mhz and 2.048 mhz clocks and 8khz frame pulse depending on the major mode selected. 0 1 provides st-bus 4.096 mhz & 2.048 mhz clocks depending on the major mode selected while f0b acts as an input. however, the input on f0b has no effect on the operation of dpll #2 unless it is in free-run mode. 0 0 overrides the major mode selected and accepts properly phase related external 4.096 mhz clock and 8 khz frame pulse to provide the st-bus compatible clock at 2.048mhz. 1 0 overrides the major mode selected and accepts a 4.096 mhz external clock to provide the st-bus clock and frame pulse at 2.048 mhz and 8 khz, respectively.
MT8940 iso-cmos 3-32 f0b (refer to figure 15). otherwise, the input on pin f0b will have no bearing on the operation of dpll #2, unless it is in free-run mode as selected by ms0 and ms1. in free-run mode, the input on f0b is treated the same way as the c8kb input in normal mode. the frequency of the input signal on f0b should be 16 khz for dpll #2 to provide the st- bus compatible clocks at 4.096 mhz and 2.048 mhz. when ms2 is high, the f0b pin provides the st- bus frame pulse output locked to the 8khz internal or external signal as determined by the other mode select pins ms0, ms1 and ms3. table 4 summarizes the modes of the two dplls. it should be noted that each of the major modes selected for dpll #2 can have any of the minor modes, although some of the combinations are functionally similar. the required operation of both dpll#1 and dpll#2 must be considered when determining ms0-ms3. table 4. summary of modes of operation - dpll #1 and #2 m o d e # ms 0 ms 1 ms 2 ms 3 operating modes dpll #1 dpll #2 0 0000 normal mode properly phase related external 4.096 mhz clock and 8 khz frame pulse provide the st- bus clock at 2.048 mhz. 1 0001 normal mode normal mode f0b is an input but has no function in this mode. 2 0010 normal mode external 4.096 mhz provides the st-bus clock and frame pulse at 2.048 mhz and 8 khz, respectively. 3 0011 normal mode: provides the t1 (1.544 mhz) clock synchronized to the falling edge of the input frame pulse ( f0i). normal mode: provides the cept/st-bus compatible timing signals locked to the 8 khz input signal (c8kb). 4 0100 divide-1 mode same as mode 0. 5 0101 divide-1 mode single clock-1 mode f0b is an input, but has no function in this mode. 6 0110 divide-1 mode same as mode 2. 7 0111 divide-1 mode: divides the cvb input by 193. the divided output is connected to dpll #2. single clock-1 mode: provides the cept/st-bus compatible timing signals locked to the 8 khz internal signal provided by dpll #1. 8 1000 normal mode same as mode 0. 9 1001 normal mode f0b is an input and dpll #2 locks on to it only if it is at 16 khz to provide the st-bus control signals. 10 1010 normal mode same as mode 2. 11 1011 normal mode provides the t1 (1.544 mhz) clock synchronized to the falling edge of input frame pulse ( f0i). free-run mode: provides the st-bus timing signals with no external inputs except the master clock. 12 1100 divide-2 mode same as mode 0. 13 1101 divide-2 mode single clock-2 mode: f0b is an input, but has no function in this mode. 14 1110 divide-2 mode same as mode 2. 15 1111 divide-2 mode: divides the cvb input by 256. the divided output is connected to dpll#2. single clock-2 mode: provides the cept/st-bus compatible timing signals locked to the 8 khz internal signal provided by dpll #1.
iso-cmos MT8940 3-33 applications the following ?gures illustrate how the MT8940 can be used in a minimum component count approach to providing the timing and synchronization signals for the mitel t1 and cept interfaces, and the st-bus. the hardware selectable modes and the independent control over each pll adds ?exibility to the interface circuits. it can be easily recon?gured to provide the timing and control signals for both at the master and slave ends of the link. synchronization and timing signals for the t1 transmission link figures 4 and 5 show examples of how to generate the timing signals for the master and slave ends of a t1 link. at the master end of the link (figure 4), dpll #2 is the source of the st-bus signals derived from the 4.096 mhz system clock. the frame pulse output is looped back to dpll #1 (in normal mode), which locks to it to generate the t1 line clock. the timing relationship between the 1.544 mhz t1 clock and the 2.048 mhz st-bus clock meets the requirements of the mh89760/760b. the crystal clock at 12.355 mhz is used by dpll #1 to generate the 1.544 mhz clock, while dpll #2 uses the 4.096 mhz system clock to provide the st-bus timing signals. the st-bus signals can also be obtained from dpll #2 in free- run mode, using a crystal clock at 16.388 mhz instead of 4.096 mhz system clock. the uncommitted nand gate converts the received signals, rxa and rxb of the mh89760 to a single return to zero (rz) input for the clock extraction circuits of the mh89760. this is not required for the mh89760b. the generated st-bus signals can be used to synchronize the system and the switching equipment at the master end. at the slave end of the link (figure 5) both the dplls are in normal mode with dpll #2 providing the st-bus timing signals locked to the 8 khz frame pulse (e8ko) extracted from the received signal on the t1 line. the regenerated frame pulse is looped back to dpll #1 to provide the t1 line clock as at the master end. the 12.355 mhz and 16.388 mhz crystal clock sources are necessary for dpll #1 and #2. synchronization and timing signals for the cept transmission link the MT8940 can be used to provide the timing and synchronization signals for the mh89790/790b, mitels cept(30+2) digital trunk interface hybrid. since the operational frequencies of the st-bus and the cept primary multiplex digital trunk are same, only dpll #2 is required to achieve synchronization between the two . figures 6 and 7 show how the MT8940 can be used to synchronize the st-bus and the cept transmission link at the master and slave ends, respectively. figure 4 - synchronization at the master end of the t1 transmission link crystal clock (12.355 mhz 100 ppm) 4.096 mhz system clock (st-bus compatible) MT8940 ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o ai bi v ss v dd cv c4b c2o f0b y o rst mh89760 c1.5i c2i f0i rxa rxb rxd dsti dsto csti csto txt txr rxt rxr mt8980/81 st-bus switch t1 link (1.544 mbps) transmit receive mode of operation for the MT8940 dpll #1 - normal (ms0 = x; ms1 = 0) dpll #2 - override the major modes (ms2 = 1; ms3 = 0)
MT8940 iso-cmos 3-34 figure 5 - synchronization at the slave end of the t1 transmission link figure 6 - synchronization at the master end of the cept digital transmission link crystal clock (12.355 mhz 100 ppm) MT8940 ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o ai bi v ss v dd cv c4b c2o f0b y o rst mh89760 c1.5i c2i f0i rxa rxb rxd dsti dsto csti csto txt txr rxt rxr mt8980/81 st-bus switch t1 link (1.544 mbps) mode of operation for the MT8940 dpll #1 - normal (ms1=0) dpll #2 - normal (ms0=0; ms1=0; ms2=1; ms3=1) crystal clock (16.388 mhz 32 ppm) transmit receive MT8940 ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o ai bi v ss v dd c4b c2o f0b y o rst mh89790 c2i f0i rxa rxb rxd dsti dsto csti0 csti1 csto outa outb rxt transmit receive mt8980/81 st-bus switch rxr cept primary multiplex digital link 4.096 mhz system clock (st-bus compatible) mode of operation for the MT8940 dpll #1 - not used dpll #2 - override major modes (ms0=x; ms1=x ms2=1; ms3=0) generation of st-bus timing signals the MT8940 can source the properly formatted st- bus timing and control signals with no external inputs except the crystal clock. this can be used as the standard timing source for st-bus systems or any other system with similar clock requirements. figure 8 shows two such applications using only dpll #2. in one case, the MT8940 is in free-run mode with an oscillator input of 16.388 mhz. this forces the dpll to correct at a rate of 4 khz to maintain the st-bus clocks, which therefore, will be jittered. in the other case, the oscillator input is 16.384 mhz (exactly eight times the output frequency) and dpll #2 operates in normal mode with c8kb input tied high. since no corrections are necessary, the output is free from jitter. dpll #1 is completely free in both cases and available for any other purpose.
iso-cmos MT8940 3-35 figure 7 - synchronization at the slave end of the cept digital transmission link figure 8 - generation of the st-bus timing signals transmit receive mt8980/81 st-bus switch mh89790 c2i f0i rxa rxb rxd dsti dsto csti0 csti1 csto outa outb rxt rxr MT8940 ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o ai bi v ss v dd c4b c2o f0b y o rst cept primary multiplex digital link crystal clock (16.388 mhz 32 ppm) mode of operation for the MT8940 dpll #1 - not used dpll #2 - normal (ms0=0; ms1=0; ms2=1; ms3=1) MT8940 ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o ai bi v ss v dd c4b rst crystal clock (16.388 mhz 32 ppm) crystal clock (16.388 mhz 32 ppm) c4o c2o c2o f0b MT8940 ms0 ms1 ms2 ms3 f0i c12i en cv c8kb c16i en c4o en c2o ai bi v ss v dd c4b rst c4o c2o c2o f0b dpll #1 - not used dpll #2 - normal mode (ms0=0; ms1=0; ms2=1; ms3=1) dpll #1 - not used dpll #2 - normal mode (ms0=0; ms1=0; ms2=1; ms3=1) st-bus timing signals st-bus timing signals
MT8940 iso-cmos 3-36 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings* - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min max units 1 supply voltage v dd -0.3 7.0 v 2 voltage on any pin v i v ss -0.5 v dd +0.5 v 3 input/output diode current i ik/ok 10 ma 4 output source or sink current i o 25 ma 5 dc supply or ground current i dd /i ss 50 ma 6 storage temperature t st -65 150 o c 7 package power dissipation lcc p d 600 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 supply voltage v dd 4.75 5.0 5.25 v 2 input high voltage v ih 2.4 v dd v for 400 mv noise margin 3 input low voltage v il v ss 0.4 v for 400 mv noise margin 4 operating temperature t a -40 25 85 o c dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. v dd =5.0 v 5%; v ss =0v; t a =-40 to 85 c. characteristics sym min typ ? max units test conditions 1 s u p supply current i dd i dds 815 100 ma under clocked condition, with the inputs tied to the same supply rail as the corresponding pull-up / down resistors. 2 i n input high voltage (for all the inputs except pin 23) v ih 2.0 v 3 positive-going threshold voltage (for pin 23) v + 2.8 v 4 input low voltage (for all the inputs except pin 23) v il 0.8 v 5 negative-going threshold voltage (for pin 23) v - 1.5 v 6 o u t output current high (for all the outputs except pin 10) i oh -9.5 ma v oh =2.4 v 7 output current low (for all the outputs except pin 10) i ol 4.5 ma v ol =0.4 v 8 output current low (pin 10) i ol 2.0 ma v ol =0.4 v 9 leakage current on bidirect- ional pins and all inputs except c12i, c16i, rst i iz/oz 150 m av i/o = v ss or v dd 10 leakage current on all outputs and c12i, c16i, rst inputs i iz/oz 1 10 m av i/o =v ss or v dd
iso-cmos MT8940 3-37 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 9 - timing information for dpll #1 in normal mode ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (ref. figure 9) characteristics sym min typ ? max units test conditions 1 d p l l #1 frame pulse input ( f0i) to cvb output (1.544 mhz) delay t f15h -40 75 ns 2 cvb output (1.544 mhz) rise time t r1.5 10 15 ns test load circuit 1 (fig. 17). 3 cvb output (1.544 mhz) fall time t f1.5 12 15 ns test load circuit 1 (fig. 17). 4 cvb output (1.544 mhz) clock period t p15 648 690 ns 5 cvb output (1.544 mhz) clock width (high) t w15h 320 386 ns 6 cvb output (1.544 mhz) clock width (low) t w15l 314 327 ns 7 cv delay (high to low) t 15hl 530ns 8 cv delay (low to high) t 15lh -12 10 ns ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (ref. figure 10) characteristics sym min typ ? max units test conditions 1 d p l l #1 c8kb output (8khz) delay (high to high) t c8hh 130 ns test load circuit 2 (fig. 17). 2 c8kb output (8 khz) delay (low to low) t c8ll 50 130 ns test load circuit 2 (fig. 17). 3 c8kb output duty cycle 66 50 % % in divide -1 mode in divide - 2 mode 4 inverted clock output delay (high to low) t ichl 40 75 ns 5 inverted clock output delay (low to high) t iclh 35 60 ns f0i cvb cv v ih v il v oh v ol v oh v ol t f15h t f1.5 t 15hl t 15lh t r1.5 t p15 t w15h t w15l
MT8940 iso-cmos 3-38 figure 10 - dpll #1 in divide mode figure 11 - timing information on dpll #2 outputs cvb cv c8kb v ih v il v oh v ol v oh v ol t ichl t iclh t c8hh t c8ll v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol f0b c4b c4o c2o c2o t fpl t fph t fc4 t rc4 t 4olh t 4ohl t 42lh t 42hl t fc2 t rc2 t 2olh t 2ohl t wfp t p2o t w2oh t w2ol
iso-cmos MT8940 3-39 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 12 - st-bus timings from dpll #2 and c8kb input/output ac electrical characteristics ? -voltages are with respect to ground (v ss ) unless otherwise stated. (ref. figures 11&12) characteristics sym min typ ? max units test conditions 1 d p l l #2 c4b output delay (high to low) from c8kb input/output t 84h -25 75 ns test load circuit 2 (fig. 17) on c8kb. 2 c4b output clock period t p4o 240 282 ns test load circuit 1 (fig. 17). 3 c4b output clock width (high) t w4oh 123 165 ns 4 c4b output clock width (low) t w4ol 110 123 ns 5 c4b output clock rise time t rc4 10 ns test load circuit 1 (fig. 17). 6 c4b clock output fall time t fc4 10 ns test load circuit 1 (fig. 17). 7 frame pulse output delay (high to low) from c4b t fpl 50 ns test load circuit 1 (fig. 17). 8 frame pulse output delay (low to high) from c4b t fph 40 ns test load circuit 1 (fig. 17). 9 frame pulse ( f0b) width t wfp 200 245 ns 10 c4o delay - low to high t 4olh 45 ns 11 c4o delay - high to low t 4ohl 45 ns 12 c4b to c2o delay (low to high) t 42lh -10 +10 ns 13 c4b to c2o delay (high to low) t 42hl 20 ns 14 c2o clock period t p2o 486 523 ns test load circuit 1 (fig. 10). 15 c2o clock width (high) t w2oh 244 291 ns 16 c2o clock width (low) t w2ol 233 244 ns 17 c2o clock rise time t rc2 10 ns test load circuit 1 (fig. 10). 18 c2o clock fall time t fc2 10 ns test load circuit 1 (fig. 10). 19 c2o delay - low to high t 2olh 20 ns 20 c2o delay - high to low t 2ohl -5 30 ns v oh v ol v oh v ol v oh v ol v ih v il c4b f0b c8kb as output c8kb as input t 84h t w4oh t p4o t fpl t fph t w4ol
MT8940 iso-cmos 3-40 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 13 - f0b from dpll #2 is looped back as input to dpll #1 (t1 line synchronized to st-bus) ? timing is over recommended temperature & power supply voltages ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 14 - master clock inputs ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (ref. figure 13) characteristics sym min typ ? max units test conditions 1 cv/cvb (1.544 mhz) setup time t s15 25 ns 2 cv/cvb (1.544 mhz) hold time t h15 110 ns ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (ref. figure 14) characteristics sym min typ ? max units test conditions 1 c l o c k s master clocks input rise time t r 10 ns 2 master clocks input fall time t f 10 ns 3 master clock period (12.355mhz) t p12 80.930 80.938 80.946 ns for dpll #1, while operating to provide the t1 clock signal. 4 master clock period (16.388mhz) t p16 61.018 61.020 61.022 ns for dpll #2, while operating to provide the cept and st-bus timing signals. 5 duty cycle of master clocks 45 50 55 % 6 lock-in range (for each pll) -1.5 +1.04 hz with the master clocks as shown above. f0b c2o cv cvb v oh v ol v oh v ol v oh v ol v oh v ol t s15 t h15 boundary between st-bus channel 2 bit 4 and channel 2 bit 3 20 cycles t h15 t s15 master clock inputs 2.4 v 1.5 v 0.4 v t r t f t p12 or t p16
iso-cmos MT8940 3-41 ? timing is over recommended temperature & power supply voltages ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 15 - external inputs on c4b and f0b for the dpll #2 ? timing is over recommended temperature & power supply voltages ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 16 - three state outputs and enable timings ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (ref. figure 15) characteristics sym min typ ? max units test conditions 1 f0b input pulse width (low) t wfp 40 ns 2 c4b input clock period t p4o .080 50 m s 3 frame pulse ( f0b) setup time t fs 25 ns 4 frame pulse ( f0b) hold time t fh 5ns ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. (ref. figure 16) characteristics sym min typ ? max units test conditions 1 o u t p u t delay from enable to output (high to three state) t phz 15 65 ns test load circuit 3 (fig.17) 2 delay from enable to output (low to three state) t plz 10 55 ns test load circuit 3 (fig.17) 3 delay from enable to output (three state to high) t pzh 40 ns test load circuit 3 (fig.17) 4 delay from enable to output (three state to low) t pzl 50 ns test load circuit 3 (fig.17) f0b c4b v ih v il v ih v il t fs t wfp t fh t p4o enable input output low to off output high to off t f 6 ns t r 6 ns 10% 90% 1.3 v 1.3 v outputs enabled outputs enabled outputs disabled 3.0 v 2.7 v 1.3 v 0.3 v t plz t phz t pzl t pzh
MT8940 iso-cmos 3-42 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. figure 17 - test load circuits ac electrical characteristics ? - uncommitted nand gate voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 propagation delay (low to high), input ai or bi to output t plh 25 40 ns test load circuit 1 (fig. 17) 2 propagation delay (high to low), input ai or bi to output t phl 20 40 ns test load circuit 1 (fig. 17) from output under test test point c l =50pf test load circuit- 1 v dd r l =1k w test point from output under test test load circuit- 2 test load circuit- 3 from output under test c l =50pf c l =50pf test point s 1 v dd v ss r l =1k w note: s 1 is in position a when measuring t plz and t pz and in position b when measuring t phz and t pzh a b
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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